1. Field of the Invention
The present invention relates to a two-step superconformal process for depositing seam-free microelectronic conductors.
2. Background
In the recent development of semiconductor fabrication technologies, the replacement of aluminum-based alloys by pure copper as a chip interconnection material results in numerous advantages in the chip performance. Conventionally, aluminum-copper and its related alloys have been used as a preferred metal conductor material for forming interconnections on electronic devices such as IC chips. The copper content in an aluminum-copper alloy is limited typically to a range between about 0.3 and about 4%.
The chip performance improvements made possible by pure copper or copper alloys includes a lower electrical resistivity since the resistivity of copper and certain copper alloys is less than the resistivity of aluminum-copper. Based on the low resistivity of copper, narrower lines can be used and higher wiring densities can also be realized.
While the advantages of copper metallization have been recognized by many in the semiconductor industry, copper metallization has been the subject of extensive research effort in recent years. Semiconductor processes such as chemical vapor deposition (CVD) and electroless plating are popularly used for depositing copper. Both of these methods of deposition produce at best conformal deposits and sometimes lead to defects such as voids in a wiring structure, especially when trenches are deposited which have a cross-section narrower at the top than at the bottom as a result of an imperfect reactive ion etching process. Similarly, while the electroless plating technique offers the advantage of low cost, the evolution of hydrogen gas during deposition leads to blistering and other void defects which are detrimental to the quality and reliability of IC devices built.
One such electroplating processes for depositing copper, silver or gold onto a semiconductor wafer is described in U.S. Pat. No. 5,256,274, herein incorporated by reference in its entirety, issued in 1993. In this patent, a copper conductor which is obtained with a seam at its center is judged as a good deposition while a copper conductor with a void at its center is judged as bad deposition. The plating bath utilized in the patent contains 12 ounces/gallon of water of CuSO4 5H2O, 10% by volume of concentrated sulfuric acid, 50 ppm of chloride ion from hydrochloric acid, and TECHNI-COPPER W additive at 0.4% by volume provided by Technic, Inc. of Providence, R.I. The resulting structures contained scams.
The electroplated copper that is presently being used as line and via level interconnections in semiconductor devices suffers from an initially high resistance which requires either a long time, i.e., three days, room temperature anneal or some shorter time elevated temperature anneal to reduce the films to acceptable resistance levels. Typically, electroplated copper films are deposited in a fine grained condition from baths that contain additives or dopants. With time, these initially small copper grains, i.e., in the range of approximately 20 nm, grow to a final large grain, i.e., in the range of 1,000nm, low stress microstructure during which time a resistance drop of approximately 20-30% occurs. The long anneal times required therefore places unacceptable limits on the fabrication process which results in a more expensive copper process. In order to speed up the fabrication processes, it is important that this grain growth and associated resistance drop, i.e., the resistance transient, occur in as short a time as possible. The large grained, low resistance, plated copper is preferred since it has both better electromigration stress voiding behavior than fine grained copper films and the desired high electrical conductivity.
The technology of making metal conductors to provide for trenches, vias, lines and other recesses in semiconductor chip structures, flat panel displays and package applications has been developed recently. For instance, in developing interconnection technology for very-large-scale-integrated (VLSI) structures, aluminum has been utilized as the primary metal source for contacts and interconnects in semiconductor regions or devices located on a single substrate. Aluminum has been the material of choice because of its low cost, good ohmic contact and high conductivity. However, pure aluminum thin-film conductors have undesirable properties such as a low melting point which limits its use to low temperature processing and possible diffusion into the silicon during annealing which leads to contact and junction failure, and poor electromigration resistance. Consequently, a number of aluminum alloys have been developed which provided advances over pure aluminum.
Recently developed ULSI (ultra large scale integration) technology has placed more stringent demands on the wiring requirements due to the extremely high circuit densities and faster operating speeds required of such devices. This leads to higher current densities in increasingly smaller conductor lines. As a result, higher conductance wiring is desired which requires either larger cross-section wires for aluminum alloy conductors or a different wiring material that has a higher conductance. The obvious choice in the industry is to develop the latter which includes pure copper for its desirable high conductivity.
In the formation of ULSI interconnection structures such as trenches, vias and lines, copper can be deposited into such recesses to interconnect semiconductor regions or devices located on the same substrate. However, copper is known to have problems in semiconductor devices. The electromigration phenomenon occurs when the superposition of an electric field onto random thermal diffusion in a metallic solid causes a net drift of atoms in the “direction of electron flow. This can lead to degradation in interconnect reliability. Diffusion of copper atoms into the silicon substrate or ILD can also cause device failure and poor reliability. In addition, pure copper does not adhere well to oxygen-containing dielectrics such as silicon dioxide and polyimide. To fully utilize copper in interconnection technology, the adhesion, diffusion and electromigration properties of copper must be improved.
More recently, void-free and seamless conductors are produced by electroplating copper from plating baths that contain additives. One such method is described by U.S. Pat. No. 6,429,523, herein incorporated by reference in its entirety. The capability of the electroplating method to superfill structural features without leaving voids or seams is unique and superior to that of other deposition techniques. Electrolytic copper plating techniques used in damascene structures can be defect-free if the deposited seed layer is continuous and has a uniform thickness even in the deepest area of the structural feature to be plated. The copper seed layer is typically deposited by a physical vapor deposition technique or other techniques over a barrier layer that prevents diffusion of copper into the insulator such as Ta, TaN, TiN or TaSiN. When the deposited seed layer is too thin at the bottom or near-bottom walls of a structural feature, plating does not occur and a void is created.
In order to eliminate the non-continuous deposition problem occurring in sputter deposited copper seed layers, a seed layer of a larger thickness is normally deposited. The deposition of a thick seed layer helps to eliminate the plated Cu voiding problem, however, it creates another one of equal or even greater significance, i.e. poor electromigration resistance in the resultant structure. The poor electromigration resistance of the structure is caused by the fact that the seed layer itself has weak electromigration resistance when compared to the much higher electromigration resistance of the plated film. It is also noted that in future generations of chips, the seed layer will contribute an increasing part of the total structure based on the decreasing dimensions of the features and the inability to decrease the thickness of the seed layer proportionally for reasons stated above as well as the thickness uniformity requirements in electrolytic plating.
The use of electrodeposited copper in integrated circuits is due, in part, to the ability of the deposition process to fill high aspect ratio features superconformally. Understanding the “superfilling” process has been complicated by the presence of both deposition rate suppressing (inhibitor) and deposition-rate accelerating (catalyst) additives in the electrolytes. Initially, efforts were made to extend leveling theory, whereby inhibitor depletion in the electrolyte within patterned features results in a nonuniform deposition rate and smoothing of the surface profile. However, it was found that this formalism failed to explain the filling process in submicrometer features and an empirically modified constitutive equation was required to simulate feature filling.
In the first such efforts the constitutive fitting equation provided the sole distinction between leveling and superfilling. Subsequently, an attempt to reconcile superfilling with a more robust description of the traditional leveling model has been accomplished. Nonetheless, comparison between these models and experimental observations revealed that superfilling could not be explained by an inhibition or leveling model.
Recently, a curvature-enhanced accelerator coverage (CEAC) mechanism has been shown to quantitatively describe superconformal film growth.
The CEAC mechanism is described in Superconformal Electrodeposition Using Derivitized Substrates, Electrochemical and Solid-State Letters, 5 (12) C110-C112 (2002), herein incorporated by reference in its entirety. In this model, the accelerator, or catalyst, is considered to displace the inhibiting halide-cuprous-polyether species from the interface and remain segregated at the interface during metal deposition. Because the growth rate is directly proportional to the catalyst coverage, these stipulations naturally give rise to “bottom-up” or superfilling of submicrometer features as the catalyst coverage and metal deposition rate steadily increase during conformal growth on a concave surface such as the bottom of a filling feature. The CEAC mechanism has been incorporated into several different shape change models and successfully predicts the initial incubation period of conformal deposition, the superconformal bottom-to-to filling itself, and the subsequent “momentum plating” or bump formation over filled features that are commonly observed. None of these aspects of filling could be explained by the leveling models. The CEAC models allow filling over the entire experimental parameter space, i.e., catalyst precursor concentration, overpotential, and feature aspect ratio, to be explored for both trench and via geometries. Furthermore, these predictions are made with no fitting parameters; all kinetic factors are obtained from deposition studies conducted on planar substrates. More recently, the generality of the CEAC model has been demonstrated by successfully describing superconformal electrodeposition of silver from a selenium catalyzed electrolyte as well as iodine catalyzed copper chemical vapor deposition.